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asix electronics corporation first released date : oct/02/1998 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http://www.asix.com.tw AX88195P 10/100base fast ethernet mac controller 10/100base local cpu bus fast ethernet mac controller document no.: ax195-17 / v1.7 / may. 12 ? 00 features ieee 802.3u 100base-t, tx, and t4 compatible single chip local cpu bus 10/100mbps fast ethernet mac controller ne2000 register level compatible instruction support both 8 bit and 16 bit local cpu interf ace s include mcs-51 series, 80186 series and mc68k series cpu support both 10mbps and 100mbps data rate support both full-duplex or half-duplex operation provides a mii port for both 10/100mbps operation support eeprom interface to store mac address external and internal loop-back capability two external 32k*8 asynchronous srams required for packet buffer 128-pin lqfp low profile package 2 5mhz operation, dual 5v and 3.3 v cmos process with 5v i/o tolerance . or pure 3.3v operation *ieee is a registered trademark of the institute of electrical and electronic engineers, inc. *all other trademarks and registered trademark are the property of their respective holders. product description the ax88195 fast ethernet controller is a high performance and highly integrated local cpu bus ethernet controller. the ax88195 supports both 8 bit and 16 bit local cpu interf ace s include mcs-51 series, 80x86 series, mc68k series cpu and isa bus. the ax88195 implements both 10mbps and 100mbps ethernet function based on ieee802.3 / ieee802.3u lan standard and supports both 10mbps/100mbps media-independent interface (mii) to simplify the design. two low cost 32k*8 sram is required for packet buffer. system block diagram always contact asix for possible updates before starting a design. this data sheet contains new products information. asix electronics reserves the rights to modify product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. cpu latch ax88195 ad bus addr l addr h ctl bus buffer sram phy/txrx rj45
asix electronics corporation 2 ax88195 local cpu bus fast ethernet mac controller contents 1.0 introduction ................................ ................................ ................................ ................................ .............. 4 1.1 g eneral d escription : ................................ ................................ ................................ ................................ ..... 4 1.2 ax88195 b lock d iagram : ................................ ................................ ................................ .............................. 4 1.3 ax88195 p in c onnection d iagram ................................ ................................ ................................ ............... 5 1.3.1 ax88195 pin connection diagram for isa bus mode ................................ ................................ ................ 6 1.3.2 ax88195 pin connection diagram for 80x86 mode ................................ ................................ ................... 7 1.3.3 ax88195 pin connection diagram for mc68k mode ................................ ................................ ................ 8 1.3.4 ax88195 pin connection diagram for mcs-51 mode ................................ ................................ ............... 9 2.0 signal description ................................ ................................ ................................ ................................ . 10 2.1 l ocal cpu b us i nterface s ignals g roup ................................ ................................ ................................ ... 10 2.2 mii interface signals group ................................ ................................ ................................ ........................ 11 2.3 eeprom s ignals g roup ................................ ................................ ................................ .............................. 12 2.4 sram i nterface pins group ................................ ................................ ................................ ......................... 12 2.5 m iscellaneous pins group ................................ ................................ ................................ ............................ 12 2.6 p ower on configuration setup signals cross reference table ................................ ................................ 13 3.0 memory and i/o mapping ................................ ................................ ................................ ...................... 14 3.1 eeprom m emory m apping ................................ ................................ ................................ .......................... 14 3.2 i/o m apping ................................ ................................ ................................ ................................ ................... 14 3.3 sram m emory m apping ................................ ................................ ................................ .............................. 14 4.0 registers operation ................................ ................................ ................................ ............................. 15 4.1 c ommand r egister (cr) o ffset 00h (r ead /w rite ) ................................ ................................ ................... 17 4.2 i nterrupt s tatus r egister (isr) o ffset 07h (r ead /w rite ) ................................ ................................ ..... 17 4.3 i nterrupt mask register (imr) o ffset 0fh (w rite ) ................................ ................................ ................. 18 4.4 d ata c onfiguration r egister (dcr) o ffset 0eh (w rite ) ................................ ................................ ....... 18 4.5 t ransmit c onfiguration r egister (tcr) o ffset 0dh (w rite ) ................................ ................................ 18 4.6 t ransmit s tatus r egister (tsr) o ffset 04h (r ead ) ................................ ................................ ................ 19 4.7 r eceive c onfiguration (rcr) o ffset 0ch (w rite ) ................................ ................................ .................. 19 4.8 r eceive s tatus r egister (rsr) o ffset 0ch (r ead ) ................................ ................................ .................. 19 4.9 i nter - frame gap (ifg) o ffset 16h (r ead /w rite ) ................................ ................................ ...................... 20 4.10 i nter - frame gap s egment 1(ifgs1) o ffset 12h (r ead /w rite ) ................................ ............................... 20 4.11 i nter - frame gap s egment 2(ifgs2) o ffset 13h (r ead /w rite ) ................................ ............................... 20 4.12 mii/eeprom m anagement r egister (memr) o ffset 14h (r ead /w rite ) ................................ .............. 20 4.13 t est r egister (tr) o ffset 15h (w rite ) ................................ ................................ ................................ ... 20 5.0 cpu i/o read and write functions ................................ ................................ ................................ .. 21 5.1 isa bus type access functions . ................................ ................................ ................................ ................... 21 5.2 80186 cpu bus type access functions . ................................ ................................ ................................ ........ 21 5.3 mc68k cpu bus type access functions . ................................ ................................ ................................ ..... 22 5.3 mcs-51 cpu bus type access functions . ................................ ................................ ................................ .... 22 6.0 electrical specification and timings ................................ ................................ ........................ 23 6.1 a bsolute m aximum r atings ................................ ................................ ................................ ........................ 23 6.2 g eneral o peration c onditions ................................ ................................ ................................ ................... 23 6.3 dc c haracteristics ................................ ................................ ................................ ................................ ..... 23 6.4 a.c. t iming c haracteristics ................................ ................................ ................................ ....................... 24 6.4.1 xtal / clock ................................ ................................ ................................ ................................ ........ 24 6.4.2 reset timing ................................ ................................ ................................ ................................ ............ 24 6.4.3 isa bus access timing ................................ ................................ ................................ ............................. 25 6.4.4 80186 type i/o access timing ................................ ................................ ................................ ................. 26
asix electronics corporation 3 ax88195 local cpu bus fast ethernet mac controller 6.4.5 68k type i/o access timing ................................ ................................ ................................ .................... 27 6.4.6 8051 bus access timing ................................ ................................ ................................ ........................... 28 6.4.7 mii timing ................................ ................................ ................................ ................................ ............... 29 6.4.8 asynchronous memory i/f access timing ................................ ................................ ................................ 30 7.0 package information ................................ ................................ ................................ ........................... 31 appendix a: application note 1 ................................ ................................ ................................ ............. 32 a.1 u sing c rystal ................................ ................................ ................................ ................................ .............. 32 a.2 u sing o scillator ................................ ................................ ................................ ................................ ......... 32 a.3 d ual power (5v and 3.3v/3.0v) application ................................ ................................ ............................. 33 a.4 s ingle power (3.3v/3.0v) application ................................ ................................ ................................ ........ 33 a.5 d ual power (5v and 3.3v) application with 3.3v phy ................................ ................................ ............. 34 appendix b: application note 2 ................................ ................................ ................................ ............. 35 b.1 a dvance a pplication for u sing c rystal ................................ ................................ ................................ ... 35 appendix c: application note for rdy is not applicable ................................ ...................... 36 errata of ax88195 v1 ................................ ................................ ................................ ................................ ..... 37 figures f ig - 1 ax88195 b lock d iagram ................................ ................................ ................................ ............................. 4 f ig - 2 ax88195 p in c onnection d iagram ................................ ................................ ................................ .............. 5 f ig - 3 ax88195 p in c onnection d iagram for isa b us m ode ................................ ................................ ............... 6 f ig - 4 ax88195 p in c onnection d iagram for 80 x 86 m ode ................................ ................................ .................. 7 f ig - 5 ax88195 p in c onnection d iagram for mc68k m ode ................................ ................................ ................ 8 f ig - 6 ax88195 p in c onnection d iagram for mcs-51 m ode ................................ ................................ ............... 9 tables t ab - 1 l ocal cpu bus interface signals group ................................ ................................ ................................ .. 11 t ab - 2 mii interface signals group ................................ ................................ ................................ ..................... 11 t ab - 3 eeprom bus interface signals group ................................ ................................ ................................ ..... 12 t ab - 4 sram i nterface pins group ................................ ................................ ................................ ...................... 12 t ab - 5 m iscellaneous pins group ................................ ................................ ................................ ......................... 13 t ab - 6 p ower on c onfiguration s etup t able ................................ ................................ ................................ ..... 13 t ab - 7 i/o a ddress m apping ................................ ................................ ................................ ................................ . 14 t ab - 8 l ocal m emory m apping ................................ ................................ ................................ ............................ 14 t ab - 9 p age 0 of mac c ore r egisters m apping ................................ ................................ ................................ .. 15 t ab - 10 p age 1 of mac c ore r egisters m apping ................................ ................................ ................................ 16
asix electronics corporation 4 ax88195 local cpu bus fast ethernet mac controller 1.0 introduction 1.1 general description: the ax88195 provides industrial standard ne2000 registers level compatable instruction set. various drivers are easy acquired, maintenance and usage. no much additional effort to be paid. software is easily port to various embedded system with no pain and tears the ax88195 fast ethernet controller is a high performance local cpu bus ethernet controller. the ax88195 supports both 8 bit and 16 bit local cpu interf ace s include mcs-51 series, 80x86 series, mc68k series cpu and isa bus. the ax88196 implements both 10mbps and 100mbps ethernet function based on ieee802.3 / ieee802.3u lan standard and supports both 10mbps/100mbps media-independent interface (mii) to simplify the design. ax88195 use 128-pin lqfp low profile package, 2 5mhz o peration, dual 5v and 3.3 v cmos process with 5v i/o tolerance or pure 3.3v operation. 1.2 ax88195 block diagram: fig - 1 ax88195 block diagram mac core sram arbiter remote dma fifos ne2000 registers host interface sta seeprom i/f sd[15:0] sa[9:0] ctl bus mii i/f memd[15:0] mema[15:1] eecs eeck eedi eedo
asix electronics corporation 5 ax88195 local cpu bus fast ethernet mac controller 1.3 ax88195 pin connection diagram the ax88195 is housed in the 128-pin plastic light quad flat pack. fig - 2 shows the ax88195 pin connection diagram. fig - 2 ax88195 pin connection diagram 123 118 122 78 70 54 41 32 24 12 8 memd[0] lvdd 117 75 57 42 26 31 21 sa[1] vss 107 105 66 65 63 60 25 16 13 3 7 vss lclk/xtalin hvdd 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 lvdd 68 58 56 55 45 23 vss 53 116 113 59 36 34 1 vss 124 108 hvdd 28 22 9 hvdd nc 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 vss vss 40 37 50 18 14 ax88195 local cpu bus 10/100base mac controller 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 tx_en tx_clk vss mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] lvdd rx_clk crs col rx_dv memd[1] memd[2] memd[3] memd[4] memd[5] memd[6] memd[7] memd[8] memd[9] memd[10] memd[11] memd[12] memd[13] memd[14] memd[15] mema[1] rx_er mema[2] mema[3] mema[4] mema[5] mema[6] mema[7] mema[8] mema[9] mema[10] mema[11] mema[12] mema[13] mema[14] mema[15] /memrd /memwr sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] /iowr sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset /bhe txd[0] txd[1] txd[2] txd[3] xtalout eedi eedo eeck eecs lvdd lvdd vss vss vss vss hvdd vss /reset rdy/dtack irq /cs sal[0] sal[1] sal[2] sah[1] sah[2] /iocs16 aen/psen /iord r/w /lds sax[0] sax[1] sax[3] sax[2] /uds 64 clko25m sah[0] nc nc nc /irq
asix electronics corporation 6 ax88195 local cpu bus fast ethernet mac controller 1.3.1 ax88195 pin connection diagram for isa bus mode fig - 3 ax88195 pin connection diagram for isa bus mode 123 118 122 78 70 54 41 32 24 12 8 memd[0] lvdd 117 75 57 42 26 31 21 sa[1] vss 107 105 66 65 63 60 25 16 13 3 7 vss lclk/xtalin hvdd 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 lvdd 68 58 56 55 45 23 vss 53 116 113 59 36 34 1 vss 124 108 hvdd 28 22 9 hvdd nc 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 vss vss 40 37 50 18 14 ax88195 local cpu bus 10/100base mac controller ( for isa bus i/f ) 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 tx_en tx_clk vss mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] lvdd rx_clk crs col rx_dv memd[1] memd[2] memd[3] memd[4] memd[5] memd[6] memd[7] memd[8] memd[9] memd[10] memd[11] memd[12] memd[13] memd[14] memd[15] mema[1] rx_er mema[2] mema[3] mema[4] mema[5] mema[6] mema[7] mema[8] mema[9] mema[10] mema[11] mema[12] mema[13] mema[14] mema[15] /memrd /memwr sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] /iowr sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset /bhe txd[0] txd[1] txd[2] txd[3] xtalout eedi eedo eeck eecs lvdd lvdd vss vss vss vss hvdd vss /reset rdy irq /cs sal[0] sal[1] sal[2] sah[1] sah[2] /iocs16 aen /iord sax[0] sax[1] sax[3] sax[2] 64 clko25m sah[0] nc nc nc
asix electronics corporation 7 ax88195 local cpu bus fast ethernet mac controller 1.3.2 ax88195 pin connection diagram for 80x86 mode fig - 4 ax88195 pin connection diagram for 80x86 mode 123 118 122 78 70 54 41 32 24 12 8 memd[0] lvdd 117 75 57 42 26 31 21 sa[1] vss 107 105 66 65 63 60 25 16 13 3 7 vss lclk/xtalin hvdd 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 lvdd 68 58 56 55 45 23 vss 53 116 113 59 36 34 1 vss 124 108 hvdd 28 22 9 hvdd nc 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 vss vss 40 37 50 18 14 ax88195 local cpu bus 10/100base mac controller (for x86 interface) 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 tx_en tx_clk vss mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] lvdd rx_clk crs col rx_dv memd[1] memd[2] memd[3] memd[4] memd[5] memd[6] memd[7] memd[8] memd[9] memd[10] memd[11] memd[12] memd[13] memd[14] memd[15] mema[1] rx_er mema[2] mema[3] mema[4] mema[5] mema[6] mema[7] mema[8] mema[9] mema[10] mema[11] mema[12] mema[13] mema[14] mema[15] /memrd /memwr sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] /iowr sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset /bhe txd[0] txd[1] txd[2] txd[3] xtalout eedi eedo eeck eecs lvdd lvdd vss vss vss vss hvdd vss /reset rdy irq /cs sal[0] sal[1] sal[2] sah[1] sah[2] nc nc /iord sax[0] sax[1] sax[3] sax[2] 64 clko25m sah[0] nc nc nc
asix electronics corporation 8 ax88195 local cpu bus fast ethernet mac controller 1.3.3 ax88195 pin connection diagram for mc68k mode fig - 5 ax88195 pin connection diagram for mc68k mode 123 118 122 78 70 54 41 32 24 12 8 memd[0] lvdd 117 75 57 42 26 31 21 sa[1] vss 107 105 66 65 63 60 25 16 13 3 7 vss lclk/xtalin hvdd 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 lvdd 68 58 56 55 45 23 vss 53 116 113 59 36 34 1 vss 124 108 hvdd 28 22 9 hvdd nc 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 vss vss 40 37 50 18 14 ax88195 local cpu bus 10/100base mac controller (for 68k interface) 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 tx_en tx_clk vss mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] lvdd rx_clk crs col rx_dv memd[1] memd[2] memd[3] memd[4] memd[5] memd[6] memd[7] memd[8] memd[9] memd[10] memd[11] memd[12] memd[13] memd[14] memd[15] mema[1] rx_er mema[2] mema[3] mema[4] mema[5] mema[6] mema[7] mema[8] mema[9] mema[10] mema[11] mema[12] mema[13] mema[14] mema[15] /memrd /memwr sd[0] sd[1] sd[2] sd[3] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset txd[0] txd[1] txd[2] txd[3] xtalout eedi eedo eeck eecs lvdd lvdd vss vss vss vss hvdd vss /reset /dtack /cs sal[0] sal[1] sal[2] sah[1] sah[2] nc nc nc r/w /lds sax[0] sax[1] sax[3] sax[2] /uds 64 clko25m sah[0] nc nc nc /irq
asix electronics corporation 9 ax88195 local cpu bus fast ethernet mac controller 1.3.4 ax88195 pin connection diagram for mcs-51 mode fig - 6 ax88195 pin connection diagram for mcs-51 mode 123 118 122 78 70 54 41 32 24 12 8 memd[0] lvdd 117 75 57 42 26 31 21 sa[1] vss 107 105 66 65 63 60 25 16 13 3 7 vss lclk/xtalin hvdd 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 lvdd 68 58 56 55 45 23 vss 53 116 113 59 36 34 1 vss 124 108 hvdd 28 22 9 hvdd nc 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 vss vss 40 37 50 18 14 ax88195 local cpu bus 10/100base mac controller (for 8051 interface) 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 tx_en tx_clk vss mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] lvdd rx_clk crs col rx_dv memd[1] memd[2] memd[3] memd[4] memd[5] memd[6] memd[7] memd[8] memd[9] memd[10] memd[11] memd[12] memd[13] memd[14] memd[15] mema[1] rx_er mema[2] mema[3] mema[4] mema[5] mema[6] mema[7] mema[8] mema[9] mema[10] mema[11] mema[12] mema[13] mema[14] mema[15] /memrd /memwr sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] /iowr sd[6] sd[4] sd[5] sd[7] reset nc txd[0] txd[1] txd[2] txd[3] xtalout eedi eedo eeck eecs lvdd lvdd vss vss vss vss hvdd vss /reset nc /cs sal[0] sal[1] sal[2] sah[1] sah[2] nc /psen /iord sax[0] sax[1] sax[3] sax[2] 64 clko25m sah[0] nc nc nc /irq nc nc nc nc nc nc nc nc
asix electronics corporation 10 ax88195 local cpu bus fast ethernet mac controller 2.0 signal description the following terms describe the ax88195 pin-out: all pin names with the ? / ? suffix are asserted low. the following abbreviations are used in following tables . i input pu pull up o output pd pull down i/o input/output p power pin od open drain 2.1 local cpu bus i nterface s ignals g roup signal type pin no. description sal [2:0] i/pd 113 ? 111 system address select low : signals sa l [2:0] are additional address signal input lines which active low enable higher i/o address decoder on c hip . sah [2:0] i/pu 116 ? 114 system address select high : signals sa h [2:0] are additional address signal input lines which active high enable higher i/o address decoder on c hip . sax [3:0] i/pu 122 ? 121 118 ? 117 system address select low/high : signals sa x [3:0] are additional address signal input lines which active low/high depend on power on setting to enable higher i/o address decoder on c hip . sa [9:1] , sa [0] /uds i 10 ? 1 system address : signals sa[9:0] are address bus input lines which lower i/o spaces on c hip . sa[0] also means upper data strobe (/uds) active low signal in 68k application mode. /bhe or /lds i 18 bus high enable or lower data strobe : bus high enable is active low signal in some 16 bit application mode which enable high bus (sd[15:8]) active. the signal also name as lower data strobe (/lds) for 68k application mode. sd[15:0] i/o 20 ? 23, 25 ? 28, 30 ? 33, 35 ? 38 system data bus : signals sd[15:0] constitute the bi-directional data bus. ireq/ ireq o 12 interrupt request : when isa bus or 80186 cpu mode is select. ireq is asserted high to indicate the host system that the chip requires host software service. when mc68k or mcs-51 cpu mode is select. / ireq is asserted low to indicate the host system that the chip requires host software service. rdy/dtack o d 125 ready : this signal is set low to insert wait states during remote dma transfer. /dtack : when motorola cpu type is select, the pin is active low inform cpu that data is accepted. /cs i 123 chip select when the /cs signal is asserted, the chip is selected . / iord i 15 i/o read : the host asserts / iord to read data from ax88195 i/o space. when motorola cpu type is select , the pin is useless. / iowr or r/w i 14 i/o write : the host asserts / iowr to write data into ax88195 i/o space. when motorola cpu type is select, the pin is active high for read operation at the same time.
asix electronics corporation 11 ax88195 local cpu bus fast ethernet mac controller /i ocs16 o d 120 i/o is 16 bit port : the /io is16 is asserted when the address at the range corresponds to an i/o address to which the c hip responds, and the i/o port addressed is capable of 16-bit access. aen or /psen i /pd 124 address enable : the signal is asserted when the address bus is available for dma cycle. when negated (low), ax88195 an i/o slave device may respond to addresses and i/o command . psen : this signal is active low for 8051 program access. for i/o device, ax88195, this signal is active high to access the chip. this signal is for 8051 bus application only. tab - 1 local cpu b us interface signals group 2.2 mii interface signals group signal type pin no. description rxd[3:0] i 90 ? 87 receive data : rxd[3:0] is driven by the phy synchronously with respect to rx_clk. crs i 85 carrier sense : asynchronous signal crs is asserted by the phy when either the transmit or receive medium is non-idle. rx_dv i 83 receive data valid : rx_dv is driven by the phy synchronously with respect to rx_clk. asserted high when valid data is present on rxd [3:0]. rx_er i 82 receive error : rx_er ,is driven by phy and synchronous to rx_clk, is asserted for one or more rx_clk periods to indicate to the port that an error has detected. rx_clk i 86 receive clock : rx_clk is a continuous clock that provides the timing reference for the transfer of the rx_dv,rxd[3:0] and rx_er signals from the phy to the mii port of the repeater. col i 84 collision : this signal is driven by phy when collision is detected. tx_en o 95 transmit enable : tx_en is transition synchronously with respect to the rising edge of tx_clk. tx_en indicates that the port is presenting nibbles on txd [3:0] for transmission. txd[3:0] o 99 ? 96 transmit data : txd[3:0] is transition synchronously with respect to the rising edge of tx_clk. for each tx_clk period in which tx_en is asserted, txd[3:0] are accepted for transmission by the phy. tx_clk i 94 transmit clock : tx_clk is a continuous clock from phy. it provides the timing reference for the transfer of the tx_en and txd[3:0] signals from the mii port to the phy. mdc o 92 station management data clock : the timing reference for mdio. all data transfers on mdio are synchronized to the rising edge of this clock. mdc is a 2.5mhz frequency clock output. mdio i/o/pu 91 station management data input / output : serial data input/output transfers from/to the phys . the transfer protocol conforms to the ieee 802.3u mii specification. tab - 2 mii interface signals group
asix electronics corporation 12 ax88195 local cpu bus fast ethernet mac controller 2.3 eeprom s ignals g roup signal type pin no. description eecs o 106 eeprom chip select : eeprom chip select signal. eeck o 107 eeprom clock : signal connected to eeprom clock pin. eedi o 108 eeprom data in : signal connected to eeprom data input pin. eedo i /pu 109 eeprom data out : signal connected to eeprom data output pin. tab - 3 eeprom bus interface signals group 2.4 sram interface pins group signal type pin no. description mema [15:1] o 43, 45 ? 48, 50 ? 53 ? 55 ? 58, 60 ? 61 sram address : memd[15:0] i/o /pu 62 ? 63, 65 ? 68, 70 ? 74, 76 ? 80 sram data : / memrd o 42 sram read / memwr o 41 sram write tab - 4 sram interface pins group 2.5 miscellaneous pins group signal type pin no. description lclk/xtalin i 103 cmos local clock : a 25mhz clock, +/- 100 ppm, 40%-60% duty cycle. crystal oscillator input : a 25mhz crystal, +/- 25 ppm can be connected across xtalin and xtalout. xtalout o 104 crystal oscillator output : a 25mhz crystal, +/- 25 ppm can be connected across xtalin and xtalout. if a single-ended external clock (lclk) is connected to xtalin, the crystal output pin should be left floating. clko25m o 101 clock output 25mhz : this clock is source from lclk/xtalin. reset i /pd 127 reset reset is active high then place ax88195 into reset mode immediately. during falling edge the ax88195 loads the power on setting data. user can select either reset or /reset for applications. / reset i /pu 126 / reset reset is active low then place ax88195 into reset mode immediately. during ris ing edge the ax88195 loads the power on setting data. user can select either reset or /reset for applications. nc n/a 13, 16, 17, 39 no connection : for manufacturing test only. lvdd p 44, 54, 100, 110, 128 power supply : +3.3v dc.
asix electronics corporation 13 ax88195 local cpu bus fast ethernet mac controller hvdd p 19, 29, 64, 75 power supply : +5v dc. note : for pure 3.3v single power solution, all the hvdd pin can connect to +3.3v. care should be taken that hvdd input power must be greater or equal ( > = ) than lvdd. vss p 11, 24, 34, 40, 49,59, 69, 81,93, 102, 105, 119 power supply : +0v dc or ground power. tab - 5 miscel laneous pins group 2.6 power on configuration setup signals cross reference table signal name share with description io_base[2:0] memd[15:13] io_base[2] io_base[1] io_base[0] io_base 0 0 0 300h 0 0 1 320h 0 1 0 340h 0 1 1 360h 1 0 0 380h 1 0 1 3a0h 1 1 0 200h 1 1 1 220h sax[3:0] memd[12:9] sax[3] address decode depends on memd[12] power on value sax[2] address decode depends on memd[11] power on value sax[1] address decode depends on memd[10] power on value sax[0] address decode depends on memd[9] power on value cpu type memd[8:7] memd[8] memd[7] cpu type 0 0 isa bus 0 1 80186 1 0 mc68k 1 1 mcs-51 (805x) all of the above signals are pull-up for default values. tab - 6 power on configuration setup table
asix electronics corporation 14 ax88195 local cpu bus fast ethernet mac controller 3.0 memory and i/o mapping there are four memory or i/o mapping used in ax88195. 1. eeprom memory mapping 2. i/o mapping 3. local memory mapping 3.1 eeprom memory mapping user can define by themselves and can access via i/o address offset 14h mii/eeprom registers 3.2 i/o mapping system i/o offset function 00 00 h 001fh mac core register tab - 7 i/o address mapping 3.3 sram memory mapping offset function 4000h 7fff ne2000 compatable mode 8 k x 16 sram buffer 0000h ffffh extension mode 32 k x 16 sram buffer tab - 8 local memory mapping
asix electronics corporation 15 ax88195 local cpu bus fast ethernet mac controller 4.0 registers operation all registers of mac core are 8-bit wide and mapped into pages which are selected by ps in the command register. page 0 (ps 1 =0 ,ps0=0 ) offset read write 00h command register ( cr ) command register ( cr ) 01h page start register ( pstart ) page start register ( pstart ) 02h page stop register ( pstop ) page stop register ( pstop ) 03h boundary pointer ( bnry ) boundary pointer ( bnry ) 04h transmit status register ( tsr ) transmit page start address ( tpsr ) 05h number of collisions register ( ncr ) transmit byte count register 0 ( tbcr0 ) 06h current page register ( cpr ) transmit byte count register 1 ( tbcr1 ) 07h interrupt status register ( isr ) interrupt status register ( isr ) 08h current remote dma address 0 ( crda0 ) remote start address register 0 ( rsar0 ) 09h current remote dma address 1 ( crda1 ) remote start address register 1 ( rsar1 ) 0ah reserved remote byte count 0 ( rbcr0 ) 0bh reserved remote byte count 1 ( rbcr1 0 0ch receive status register ( rsr ) receive configuration register ( rcr ) 0dh frame alignment errors ( cntr0 ) transmit configuration register ( tcr ) 0eh crc errors ( cntr1 ) data configuration register ( dcr ) 0fh missed packet errors ( cntr2 ) interrupt mask register ( imr ) 10h 11h data port data port 12h ifgs1 ifgs1 13h ifgs2 ifgs2 14h mii/eeprom access mii/eeprom access 15h - test register 16h inter-frame gap ( ifg ) inter-frame gap ( ifg ) 17h to 1eh reserved reserved 1fh reset reserved tab - 9 page 0 of mac core registers mapping
asix electronics corporation 16 ax88195 local cpu bus fast ethernet mac controller page 1 ( ps1=0, ps 0 =1) offset read write 00h command register ( cr ) command register ( cr ) 01h physical address register 0 ( para0 ) physical address register 0 ( par0 ) 02h physical address register 1 ( para1 ) physical address register 1 ( par1 ) 03h physical address register 2 ( para2 ) physical address register 2 ( par2 ) 04h physical address register 3 ( para3 ) physical address register 3 ( par3 ) 05h physical address register 4 ( para4 ) physical address register 4 ( par4 ) 06h physical address register 5 ( para5 ) physical address register 5 ( par5 ) 07h current page register ( cpr ) current page register ( cpr ) 08h multicast address register 0 ( mar0 ) multicast address register 0 ( mar0 ) 09h multicast address register 1 ( mar1 ) multicast address register 1 ( mar1 ) 0ah multicast address register 2 ( mar2 ) multicast address register 2 ( mar2 ) 0bh multicast address register 3 ( mar3 ) multicast address register 3 ( mar3 ) 0ch multicast address register 4 ( mar4 ) multicast address register 4 ( mar4 ) 0dh multicast address register 5 ( mar5 ) multicast address register 5 ( mar5 ) 0eh multicast address register 6 ( mar6 ) multicast address register 6 ( mar6 ) 0fh multicast address register 7 ( mar7 ) multicast address register 7 ( mar7 ) 10h 11h data port data port 12h inter-frame gap segment 1 ifgs1 inter-frame gap segment 1 ifgs1 13h inter-frame gap segment 2 ifgs2 inter-frame gap segment 2 ifgs2 14h mii/eeprom access mii/eeprom access 15h - test register 16h inter-frame gap ( ifg ) inter-frame gap ( ifg ) 17h to 1eh reserved reserved 1fh reset rese rved tab - 10 page 1 of mac core registers mapping
asix electronics corporation 17 ax88195 local cpu bus fast ethernet mac controller 4.1 command register (cr) offset 00h (read/write) field name description 7 :6 ps 1,ps0 ps 1,ps0 : page select the two bit selects which register page is to be accessed. ps1 ps0 0 0 page 0 0 1 page 1 5:3 rd2,rd1 ,rd0 rd2,rd1,rd0 : remote dma command these three encoded bits control operation of the remote dma channel. rd2 could be set to abort any remote dma command in process. rd2 is reset by ax88195 when a remote dma has been completed. the remote byte count should be cleared when a remote dma has been aborted. the remote start address are not restored to the starting address if the remote dma is aborted. rd2 rd1 rd0 0 0 0 not allowed 0 0 1 remote read 0 1 0 remote write 0 1 1 not allowed 1 x x abort / complete remote dma 2 txp txp : transmit packet this bit could be set to initiate transmission of a packet 1 start start : this bit is used to active ax88195 operation. 0 stop stop : stop ax88195 this bit is used to stop the ax88195 operation. 4.2 interrupt status register (isr) offset 07h (read/write) field name description 7 rst reset status : set when ax88195 enters reset state and cleared when a start command is issued to the cr. writing to this bit is no effect. 6 rdc remote dma complete set when remote dma operation has been completed 5 cnt counter overflow set when msb of one or more of the tally counters has been set. 4 ovw overwrite : set when receive buffer ring storage resources have been exhausted. 3 txe transmit error set when packet transmitted with one or more of the following errors n excessive collisions n fifo underrun 2 rxe receive error indicates that a packet was received with one or more of the following errors crc error frame alignment error fifo overrun missed packet 1 ptx packet transmitted indicates packet transmitted with no error 0 prx packet received indicates packet received with no error.
asix electronics corporation 18 ax88195 local cpu bus fast ethernet mac controller 4.3 interrupt mask register (imr) offset 0fh (write) field name description 7 - reserved 6 rdce dma complete interrupt enable. default ? low ? disabled. 5 cnte counter overflow interrupt enable. default ? low ? disabled. 4 ovwe overwrite interrupt enable. default ? low ? disabled. 3 txee transmit error interrupt enable. default ? low ? disabled. 2 rxee receive error interrupt enable. default ? low ? disabled. 1 ptxe packet transmitted interrupt enable. default ? low ? disabled. 0 prxe packet received interrupt enable. default ? low ? disabled. 4.4 data configuration register ( dcr ) offset 0eh (write) field name description 7 rdcr remote dma always completed 6:2 - reserved 1 bos byte order select 0: ms byte placed on ad15:ad8 and ls byte on ad7-ad0 (80186). 1: ms byte placed on ad7::ad0 and ls byte on ad15:ad0(mc68k) 0 wts word transfer select 0 : selects byte-wide dma transfers. 1 : selects word-wide dma transfers. 4.5 transmit configuration register (tcr) offset 0dh (write) field name description 7 fdu full duplex : this bit indicates the current media mode is full duplex or not. 0 : half duplex 1 : full duplex 6 pd pad disable 0 : pad will be added when packet length less than 60. 1 : pad will not be added when packet length less tha n 60. 5 rlo retry of late collision 0 : don ? t retransmit packet when late collision happens. 1 : retransmit packet when late collision happens. 4:3 - reserved 2:1 lb1,lb0 encoded loop-back control these encoded configuration bits set the type of loop-back that is to be performed. lb1 lb0 mode 0 0 0 normal operation mode 1 0 1 internel nic loop-back mode 2 1 0 phycevisor loop-back 0 crc inhibit crc 0 : crc appended by transmitter. 1 : crc inhibited by transmitter.
asix electronics corporation 19 ax88195 local cpu bus fast ethernet mac controller 4.6 transmit status register (tsr) offset 04h (read) field name description 7 owc out of window collision 6:4 - reserved 3 abt transmit aborted indicates the ax88195 aborted transmission because of excessive collision. 2 col transmit collided indicates that the transmission collided at least once with another station on the network. 1 - reserved 0 ptx packet transmitted indicates transmission without error. 4.7 receive configuration (rcr) offset 0ch (write) field name description 7 - reserved 6 intt interrupt tri g ger mode for isa and 80186 modes 0 : low active 1 : high active (default) interrupt tri g ger mode for mcs-51 and mc68k modes 0 : high active 1 : low active (default) 5 mon monitor mode 0 : normal operation 1 : monitor mode, the input packet will be checked on node address and crc but not buffered into memory. 4 pro pro : promiscuous mode enable the receiver to accept all packets with a physical address. 3 am am : accept multicast enable the receiver to accept packets with a multicast address. that multicast address must pass the hashing array. 2 ab ab : accept broadcast enable the receiver to accept broadcast packet. 1 ar ar : accept runt enable the receiver to accept runt packet. 0 sep sep : save error packet enable the receiver to accept and save packets with error. 4.8 receive status register (rsr) offset 0ch (read) field name description 7 - reserved 6 dis receiver disabled 5 phy multicast address received. 4 mpa missed packet 3 fo fifo overrun 2 fae frame alignment error. 1 cr crc error. 0 prx packet received intact
asix electronics corporation 20 ax88195 local cpu bus fast ethernet mac controller 4.9 inter-frame gap (ifg) offset 16h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap . default value 15h. 4.10 inter-frame gap segment 1 ( ifgs1 ) offset 12h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap segment 1 . default value 0ch. 4.11 inter-frame gap segment 2 ( ifgs2 ) offset 13h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap segment 2 . default value 11h. 4.12 mii/eeprom management register ( memr ) offset 14h (read/write) field name description 7 eeclk eeclk : eeprom clock 6 eeo eeo : (read only) eeprom data out value. that reflects pin-109 eedo value. 5 eei eei eeprom data in . that output to pin-108 eedi as eeprom data input value. 4 eecs eecs eeprom chip select 3 mdo mdo mii data out 2 mdi mdi : (read only) mii data in . that reflects pin-91 mdio value. 1 m dir mii sta mdio signal direction mii read control bit, assert this bit let mdio signal as the input signal. deassert this bit let mdio as output signal. 0 mdc mdc mii clock 4.13 test register (tr) offset 15h (write) field name description 7:5 - reserved 4 tf16t test for collision 3 tpe test pin enable 2:0 ifg select test pins output
asix electronics corporation 21 ax88195 local cpu bus fast ethernet mac controller 5.0 cpu i/o read and write functions the ax88195 supports four kinds of cpu/bus types access function, including isa, 80186, mc68000 and mcs-51. these access methods are described as the following sections. 5.1 isa bus type access functions. isa bus i/o read function function mode /cs /bhe a0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x x x high-z high-z byte access l l h h l h l l h h not valid not valid even-byte odd-byte word access l l l l h odd-byte even-byte isa bus i/o write function function mode /cs /bhe a0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x x x x x byte access l l h h l h h h l l x x even-byte odd-byte word access l l l h l odd-byte even-byte 5.2 80186 cpu bus type access functions. 80186 cpu bus i/o read function function mode /cs /bhe a0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x x x high-z high-z byte access l l h l l h l l h h not valid odd-byte even-byte not valid word access l l l l h odd-byte even-byte 80186 cpu bus i/o write function function mode /cs /bhe a0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x x x x x byte access l l h l l h h h l l x odd-byte even-byte x word access l l l h l odd-byte even-byte
asix electronics corporation 22 ax88195 local cpu bus fast ethernet mac controller 5.3 mc68k cpu bus type access functions. 68k bus i/o read function function mode /cs /uds /lds r/w sd[15:8] sd[7:0] standby mode h x x x high-z high-z byte access l l h l l h h h not valid even-byte odd-byte not valid word access l l l h even-byte odd-byte 68k bus i/o write function function mode /cs /uds /lds r/w sd[15:8] sd[7:0] standby mode h x x x x x byte access l l h l l h l l x even-byte odd-byte x word access l l l l even-byte odd-byte 5.3 mcs-51 cpu bus type access functions. 8051 bus i/o read function function mode /cs /psen sa0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x l x x x x x x high-z high-z high-z high-z byte access l l h h l h l l h h not valid not valid even-byte odd-byte 8051 bus i/o write function function mode /cs /psen sa0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x l x x x x x x x x x x byte access l l h h l h h h l l x x even-byte odd-byte
asix electronics corporation 23 ax88195 local cpu bus fast ethernet mac controller 6.0 electrical specification and timings 6.1 absolute maximum ratings description sym min max units operating temperature ta 0 +85 c storage temperature ts -55 +150 c supply voltage hvdd -0.3 +6 v supply voltage lvdd -0.3 +4.6 v input voltage hvin lvin -0.3 -0.3 hvdd+0.5 lvdd+0.5 v v output voltage hvout lvin -0.3 -0.3 hvdd+0.5 lvdd+0.5 v v lead temperature (soldering 10 seconds maximum) tl -55 +220 c note : stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability. note : the power supply voltages must always fulfill hvdd >= lvdd inequality. 6.2 general operation conditions description sym min tpy max units operating temperature ta 0 25 +75 c supply voltage hvdd lvdd +4.75v +2.70 +3.00 +5.00v +3.00 +3.30 +5.25v +3.30 +3.60 v v v note : the power supply voltages must always fulfill hvdd >= lvdd inequality. 6.3 dc characteristics (vdd=5.0v, vss=0v, ta=0 c to 75 c) description sym min tpy max units low input voltage vil - 0.8 v high input voltage vih 2 - v low output voltage vol - 0.4 v high output voltage voh vdd-0.4 - v input leakage current iil -1 +1 ua output leakage current iol -1 +1 ua (vdd=3.0v to 3.6v, vss=0v, ta=0 c to 75 c) description sym min tpy max units low input voltage vil - 0.8 v high input voltage vih 1.9 - v low output voltage vol - 0.4 v high output voltage voh vdd-0.4 - v input leakage current iil -1 +1 ua output leakage current iol -1 +1 ua description sym min tpy max units power consumption (dual power) dpt5v dpt3v 20 38 ma ma power consumption (single power 3.3v) spt3v 46 ma
asix electronics corporation 24 ax88195 local cpu bus fast ethernet mac controller 6.4 a.c. timing characteristics 6.4.1 xtal / clock lclk/xtalin tr tf tlow clk25m tod symbol description min typ. max units t cyc cycle time 40 ns t high clk high time 16 20 24 ns t low clk low time 16 20 24 ns t r/ t f clk slew rate 1 - 4 ns tod lclk/xtalin to clk25m out delay (inverted) 1 3 6 ns 6.4.2 reset timing lclk /xtalin reset /reset symbol description min typ. max units trst reset pulse width 100 - - lclk tcyc thigh
asix electronics corporation 25 ax88195 local cpu bus fast ethernet mac controller 6.4.3 isa bus access timing tsu(aen) th(aen ) aen tsu(a) th(a) /bhe sa[9:0],sal,sah,sax tv(cs16-a) tdis(cs16-a) /iocs16 ten(rd) /iowr,/iord tw(rw) tv(rdy) tdis(rdy) rdy tdis(rd) read data sd[15:0](dout) data valid tsu(wr) th(wr) write data sd[15:0](din) data input establish symbol description min typ. max units t su(a) address setup time 0 - - ns t h(a) address hold time 5 - - ns t su(aen) aen setup time 0 - - ns t h(aen) aen hold time 5 - - ns t v(cs16-a) /iocs16 valid from address change - - 20 ns t dis(cs16-a) /iocs16 disable from address change - - 6 ns t v(rdy) rdy valid from /iord or /iowr - - 20 ns t dis(rdy) rdy disable from /iord or /iowr 0 - - ns t en(rd) output enable time from /iord - - 20 ns t dis(rd) output disable time from /iord 0.5 - 4 ns t su(wr) data setup time 5 - - ns t h(wr) data hold time 5 - - ns tw(rw) /iord or /iowr width time *90 ns * note : for byte access minimum is 90ns, for word access minimum is 50 ns.
asix electronics corporation 26 ax88195 local cpu bus fast ethernet mac controller 6.4.4 80186 type i/o access timing tsu(a) th(a) /bhe sa[9:0],sal,sah,sax tw(rw) /iowr,/iord tv(rdy) tdis(rdy) rdy ten(rd) tdis(rd) read data sd[15:0](dout) data valid tsu(wr) th(wr) write data sd[15:0](din) data input establish symbol description min typ. max units t su(a) address setup time 0 - - ns t h(a) address hold time 5 - - ns t v(rdy) rdy valid from /iord or /iowr - - 20 ns t dis(rdy) rdy disable from /iord or /iowr 0 - - ns t en(rd) output enable time from /iord - - 20 ns t dis(rd) output disable time from /iord 0.5 - 4 ns t su(wr) data setup time 5 - - ns t h(wr) data hold time 5 - - ns tw(rw) /iord or /iowr width time *90 ns * note : for byte access minimum is 90ns, for word access minimum is 50 ns.
asix electronics corporation 27 ax88195 local cpu bus fast ethernet mac controller 6.4.5 68k type i/o access timing tsu(a) th(a) sa[9:1],sal,sah,sax tv(ds-wr) tw(ds) tdis(wr-ds) /uds,/lds (read) r/w ten(ds) (write) r/w tv(dtack) tdis(dtack) /dtack tdis(ds) (read data) sd[15:0](dout) data valid tsu(ds) th(ds) (write data) sd[15:0](din) data input establish symbol description min typ. max units t su(a) address setup time 0 - - ns t h(a) address hold time 5 - - ns t v(ds-wr) /uds or /lds valid from /w 0 - - ns t dis(wr-ds) /w disable from /uds or /lds 5 - - ns t v(dtack) dack valid from /uds or /lds - - 20 ns t dis(dtack) dack disable from /uds or /lds 0 - - ns t en(ds) output enable time from /uds or /lds - - 20 ns t dis(ds) output disable time from /uds or /lds 0.5 - 4 ns t su(ds) data setup time 5 - - ns t h(ds) data hold time 5 - - ns tw(ds) /uds or /lds width time *90 ns * note : for byte access minimum is 90ns, for word access minimum is 50 ns.
asix electronics corporation 28 ax88195 local cpu bus fast ethernet mac controller 6.4.6 8051 bus access timing /psen tsu(psen) th(psen) tsu(a) th(a) sa[9:0],sal,sah,sax ten(rd) /iowr,/iord tw(rw) tv(rdy) tdis(rdy) (for reference) rdy tdis(rd) read data sd[7:0](dout) data valid tsu(wr) th(wr) write data sd[7:0](din) data input establish symbol description min typ. max units t su(a) address setup time 0 - - ns t h(a) address hold time 5 - - ns t su(psen) /psen setup time 0 - - ns t h(psen) /psen hold time 5 - - ns t en(rd) output enable time from /iord - - 20 ns t dis(rd) output disable time from /iord 0.5 - 4 ns t su(wr) data setup time 5 - - ns t h(wr) data hold time 5 - - ns tw(rw) /iord or /iowr width time 90 ns
asix electronics corporation 29 ax88195 local cpu bus fast ethernet mac controller 6.4.7 mii timing ttclk ttch ttcl txclk ttv tth txd<3:0> txen trclk trch trcl rxclk trs trh rxd<3:0> rxdv trs1 rxer symbol description min typ. max units ttclk cycle time(100mbps) - 40 - ns ttclk cycle time(10mbps) - 400 - ns ttch high time(100mbps) 14 - 26 ns ttch high time(10mbps) 140 - 260 ns trch low time(100mbps) 14 - 26 ns trch low time(10mbps) 140 - 260 ns ttv clock to data valid - - 20 ns tth data output hold time 5 - - ns trclk cycle time(100mbps) - 40 - ns trclk cycle time(10mbps) - 400 - ns trch high time(100mbps) 14 - 26 ns trch high time(10mbps) 140 - 260 ns trcl low time(100mbps) 14 - 26 ns trcl low time(10mbps) 140 - 260 ns trs data setup time 6 - - ns trh data hold time 10 - - ns trs1 rxer data setup time 10 - - ns
asix electronics corporation 30 ax88195 local cpu bus fast ethernet mac controller 6.4.8 asynchronous memory i/f access timing memory write tsu(a) th(a) mema[15:1] tw(wr) /memwr td(wtor) tw(rddis) /memrd tsu(d) th(d) write data sd[15:0](dout) data valid symbol description min typ. max units t su(a) address setup time 36 - - ns t h(a) address hold time 0.3 - 1 ns t w(wr) write pulse width * - ns t w(rddis) read disable pulse width * - ns t d(wtor) write to read dealy 1 - 4.5 ns t su(d) data setup time 16 - - ns t h(d) data hold time 0.3 - 2 ns memory read tsu(a) th(a) mema[15:1] referance tw(rd) internal ? /memrd ? ( high level ) /memwr ( low level ) /memrd tsu(rd) th(rd) read data memd[15:1] valid data symbol description min typ. max units t su(a) address setup time 30 - - ns t h(a) address hold time 1.3 - 1 ns t w(rd) read pulse width * - ns t su(d) data setup time 3 - - ns t h(d) data hold time 0 - 2 ns * note : the pulse width can be seen as lclk/xtalin high time. see also 6.4.1 ? thigh ? parameter. note : all most any brand asynchronous sram access time under 20 ns can fit into the specification.
asix electronics corporation 31 ax88195 local cpu bus fast ethernet mac controller 7.0 package information b e d hd e he pin 1 a2 a1 l l1 q a milimeter symbol min. nom max a1 0.1 a2 1.3 1.4 1.5 a 1.7 b 0.155 0.16 0.26 d 13.90 14.00 14.10 e 13.90 14.00 14.10 e 0.40 hd 15.60 16.00 16.40 he 15.60 16.00 16.40 l 0.30 0.50 0.70 l1 1.00 q 0 10
asix electronics corporation 32 ax88195 local cpu bus fast ethernet mac controller appendix a: application note 1 a.1 using crystal ax88195 to phy clko25m xtalin xtalout 25mhz crystal 8pf 2mohm 8pf note : the capacitors (8pf) may be various depend on the specification of crystal. while designing, please refer to the suggest circuit provided by crystal supplier. a.2 using oscillator ax88195 to phy clko25m xtalin xtalout nc 3.3v power osc 25mhz
asix electronics corporation 33 ax88195 local cpu bus fast ethernet mac controller a.3 dual power (5v and 3.3v/3.0v) application +5v +5v +5v hvdd +5v +3.3v lvdd +5v a.4 single power (3.3v/3.0v) application +3.3v +3.3v +3.3v hvdd +3.3v +3.3v lvdd +3.3v ax88195 phy/txrx magnetic rj45 +5v cpu i/f optional eeprom sram ax88195 phy/txrx magnetic rj45 +3.3v cpu i/f optional eeprom sram
asix electronics corporation 34 ax88195 local cpu bus fast ethernet mac controller a.5 dual power (5v and 3.3v) application with 3.3v phy the 510 and 1k ohm resisters are just for voltage adjustment ax88195 phy rxd[3:0] crs rx_dv rx_er rx_clk col tx_en txd[3:0] tx_clk mdc mdio rxd[3:0] crs rx_dv rx_er rx_clk col tx_en txd[3:0] tx_clk mdc mdio 510 ohm 1k ohm
asix electronics corporation 35 ax88195 local cpu bus fast ethernet mac controller appendix b: application note 2 b.1 advance application for using crystal date: may 21, 1999 condition : in short cable, ax88195 +ah 101 phyceiver can ? t link to bcm 5308 switch. conclusion : 1. after measuring and verifying, we found it ? s relevant to clock source . 2. we ascertain the problem is caused by matching issues between crystal and capacitor . solution : change the value of capacitors beside crystal as below : note: the capacitors may be various depend on the specification of crystal. while designing , please refer to the circuit provided by crystal supplier . xin xout y1 25mhz c22 18p c23 18p r4 2m
asix electronics corporation 36 ax88195 local cpu bus fast ethernet mac controller appendix c: application note for rdy is not applicable this application note is for some kind of cpu that doesn ? t support asynchronous wait state insertion function. for example, 8051 cpu series have only fix access cycle time. for some application that the cpu has the capability of wait state insertion, but the designer do not want to use the handshake signal in order to simply the design. this application note is helpful for those cases. the following criteria must be meet: 1. the bus access timing must meet the ac timing specification. 2. the ? remote dma ? move data from/to data port access time can ? t faster than 120ns. solution: because of the access time from fifo to packet buffer ram or from packet buffer ram to fifo is 120ns/word. the ? remote dma read ? operation is the only case that rdy signal will be active to request some wait state to pre-fetch data from ram into fifo. as soon as the first word of data feed into the fifo, the rdy will not active again for the lasting cycle. for the critical time, just insert ? no operation ? instruction (to insert wait state using software) after write remote dma read command and before read data port. ex : iobase=300 ; insert wait state by software. mov dx,308h ; index = 308h mov al,0h ; out dx,al ; set remote start address low byte = 0 inc dx ; index = 309h mov al,4dh ; out dx,al ; set remote start address h igh byte = 4d inc dx ; index = 30ah mov al,40h ; out dx,al ; set remote dma byte count low byte = 40h inc dx ; index = 30bh mov al,40h ; out dx,al ; set remote dma byte count high byte = 00h mov dx,300h ; index = 300h mov al,0ah ; o ut dx,al ; set remote dma read command nop ; insert wait state here nop ; insert more wait states again if necessary mov dx,310h ; index = 310h lea di, rxbuffer ; set rx buffer address mov cx, rxlen ; set rx length rep insw ; read data port ?
asix electronics corporation 37 ax88195 local cpu bus fast ethernet mac controller errata of ax88195 v1 1. interrupt status can ? t always clean up solution : using software to do clean and check iteration until clean up. ex : iobase=300 ; clear tx/rx interrupt. mov dx,307h clrisr : mov al,3 ; clear tx/rx interrupt out dx,al ; output to clear isr in al,dx ; read isr test al,3 ; check isr cleared or not jz clrisrdone ; clear ok mov al,0 ; if not, clear again out dx,al jmp clrisr clrisrdone: ? ; clear successful 2. dtack can ? t fit 68k cpu timing in 68k mode solution : using the dtack automatic insertion function in 68k cpu.

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